It is a major problem in pulse generator and integrated circuit tester technology to generate pulses of short or extremely short width, short rise and fall times and at high repetition rates.
A known technique to generate such short pulses of variable width uses a pulse start signal and a pulse stop signal, the latter being delayed in known manner with reference to the pulse stop signal. The pulse start signal is fed to the "set" terminal of a flip-flop and the pulse stop signal to the "reset" terminal of said flip-flop. Therefore, the width of the output pulse is defined by the delay between the pulse start and the pulse stop signal.
In this circuit, the minimum output pulse width is determined by the minimum pulse width of the input pulses, and, if the input pulses would overlap, the flip-flop would enter into a logically undefined state. Therefore, the input pulses must be as short as possible.
Other aspects which limit the minimum output pulse width are the recovery time and the set-up time of the flip-flop. As it is not possible to specify the pulse width of the input pulses beyond a certain range, the output pulse width contains also an element of uncertainty.
The shortest output pulse width attainable with the known formatter circuit is in the range of 3 nanoseconds (ns) using 100k ECL logic, and, with respect to the uncertainty discussed above, in the range of 5 ns. This is true for both positive and negative pulses.